`ifndef _ral_reg_REG_PRJ_sys_status_blk_status_rtl_
`define _ral_reg_REG_PRJ_sys_status_blk_status_rtl_

`include "vmm_ral_ro_field_rtl.sv"
`include "vmm_ral_notifier_rtl.sv"


module ral_reg_REG_PRJ_sys_status_blk_status_rtl(input  clk,
                              input  rstn,
                              input  [31:0] hst_wdat,
                              output [31:0] hst_rdat,
                              input  [3:0] hst_sel,
                              input  hst_wen,
                              input  [0:0] blk0_status_in,
                              output blk0_status_rd,
                              input  [0:0] blk1_status_in,
                              output blk1_status_rd,
                              input  [0:0] blk2_status_in,
                              output blk2_status_rd,
                              input  [0:0] blk3_status_in,
                              output blk3_status_rd,
                              input  [0:0] blk4_status_in,
                              output blk4_status_rd);

wire [0:0] blk0_status_out;
vmm_ral_ro_field_rtl #(1)
   blk0_status(clk, rstn, blk0_status_in, blk0_status_out);

wire [0:0] blk1_status_out;
vmm_ral_ro_field_rtl #(1)
   blk1_status(clk, rstn, blk1_status_in, blk1_status_out);

wire [0:0] blk2_status_out;
vmm_ral_ro_field_rtl #(1)
   blk2_status(clk, rstn, blk2_status_in, blk2_status_out);

wire [0:0] blk3_status_out;
vmm_ral_ro_field_rtl #(1)
   blk3_status(clk, rstn, blk3_status_in, blk3_status_out);

wire [0:0] blk4_status_out;
vmm_ral_ro_field_rtl #(1)
   blk4_status(clk, rstn, blk4_status_in, blk4_status_out);


vmm_ral_notifier_rtl _n_blk0_status(clk, rstn, hst_sel[0], hst_wen, blk0_status_rd, /*open*/);
vmm_ral_notifier_rtl _n_blk1_status(clk, rstn, hst_sel[0], hst_wen, blk1_status_rd, /*open*/);
vmm_ral_notifier_rtl _n_blk2_status(clk, rstn, hst_sel[0], hst_wen, blk2_status_rd, /*open*/);
vmm_ral_notifier_rtl _n_blk3_status(clk, rstn, hst_sel[0], hst_wen, blk3_status_rd, /*open*/);
vmm_ral_notifier_rtl _n_blk4_status(clk, rstn, hst_sel[0], hst_wen, blk4_status_rd, /*open*/);


assign hst_rdat[31:0] = { blk4_status_out, blk3_status_out, blk2_status_out, blk1_status_out, blk0_status_out };


endmodule

`endif
